The present invention relates to a method of manufacturing a semiconductor device using an organic substrate or the like and particularly to a method of sealing a chip size package (CSP) at a wafer level with a resin.
While a variety of types are known for wafer levels CSP, a wafer level CSP with an encapsulating layer, which makes use of a rewiring technology, will now be described by way of example. Incidentally, the wafer level CSP with the encapsulating layer utilizing the rewiring technology has been disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-244372, 2001-127095, etc.
In such a wafer level CSP, each of semiconductor chips on a semiconductor wafer includes metal pads disposed at its peripheral portion. An insulating layer is formed on the metal pads. Copper posts are formed on the insulating layer placed inside the metal pads. The metal pads and the copper posts are electrically connected to one another by copper conductive patterns. Since the copper conductive patterns are routed for connection to the copper posts over the insulating layer via the insulating layer, they are called xe2x80x9crewiringsxe2x80x9d.
Thereafter, an encapsulating resin such as a thermosetting epoxy is formed so as to cover the copper conductive patterns and the side faces of the copper posts. With a view toward improving the adhesion between the encapsulating resin and the insulating layer and the adhesion between each of the copper conductive patterns and its corresponding copper post, ashing or an ashing process is effected on the insulating layer, copper conductive patterns and copper posts by an argon gas, an oxygen gas or the like.
This ashing is generally done in a short period of time equivalent to within one minute at a temperature of 100xc2x0 C. or less. The exposed copper conductive patterns and copper posts are considered to be oxidized owing to such ashing in principle. While, however, its mechanism is unknown, an oxide film is actually almost unformed on the surfaces of the exposed copper conductive patterns and copper posts.
However, such ashing encounters difficulties in simultaneously ensuring both the adhesion between the insulating layer and the encapsulating resin and the adhesion between the copper and the encapsulating resin. Even if only one thereof is taken into consideration, it is difficult to ensure the adhesion between the insulating layer high in adsorbability in particular and the encapsulating resin or between the copper and the encapsulating resin.
This is ascribable to the fact that conditions for ashing are different according to materials for the insulating layer and the encapsulating resin, and adjustments thereto are difficult, particularly, the optimization of the adhesion to the copper becomes difficult.
A problem also arises in that a condition for storing a post-ashing wafer, and a restriction up to resin encapsulation are provided, and the degree of adhesion to the copper is hardly obtained when how to handle the wafer is poor.
The present invention aims to solve the foregoing problems. It is an object of the present invention to provide a method of manufacturing a semiconductor device, which is capable of simultaneously ensuring both the adhesion between an insulating layer and an encapsulating resin and the adhesion of copper and the encapsulating resin.
A method of manufacturing a semiconductor device, according to the present invention is characterized by forming copper conductive patterns on an insulating layer formed on a semiconductor base, ashing the whole insulating layer including the copper conductive patterns at a temperature at which the copper conductive patterns are not subject to oxidation, and thereafter baking the whole insulating layer including the copper conductive patterns in an oxidative atmosphere at over 150xc2x0 C. to under 200xc2x0 C. After this baking step, an encapsulating resin is formed on the insulating layer including the copper conductive patterns.